8t sram cell with higher voltage on the read wl

ABSTRACT

The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor.

This application is a continuation of application Ser. No. 12/820,960,filed Jun. 22, 2010, which is a continuation of application Ser. No.12/137,598, filed Jun. 12, 2008 (now U.S. Pat. No. 7,742,326), which isdivision of application Ser. No. 11/445,428, filed Jun. 1, 2006 (nowU.S. Pat. No. 7,400,523), the entireties of both of which are herebyincorporated herein by reference.

BACKGROUND

The present invention relates generally to semiconductor memory devices,and more particularly to an improved stability SRAM memory cell having aread buffer circuit that permits a higher read voltage and currentisolated from the latch nodes of the cell during read operations whilepermitting a lower write voltage that avoid upsets to the cell duringwrite operations.

Current trends in the semiconductor and electronics industry requirememory devices to be made smaller, faster and require less powerconsumption. One reason for these trends is that more personal devicesare being manufactured that are relatively small and portable, therebyrelying on battery power. In addition to being smaller and moreportable, personal devices are also requiring increased memory and morecomputational power and speed. In light of all these trends, there is anever increasing demand in the industry for smaller, faster, and lowerpower dissipation memory cells and transistors used to provide the corefunctionality of these memory devices.

Semiconductor memories can, for example, be characterized as volatilerandom access memories (RAMs) or nonvolatile read only memories (ROMs),where RAMs can either be static (SRAM) or dynamic (DRAM) differingmainly in the manner by which they store a state of a bit. In SRAM, forexample, each memory cell includes transistor-based circuitry thatimplements a bistable latch, which relies on transistor gain andpositive (e.g., reinforcing) feedback so that it can only assume one oftwo possible states, namely on (state 1) or off (state 2). The latch canonly be programmed or induced to change from one state to the otherthrough the application of a voltage or other external stimuli. Thisarrangement is desirable for a memory cell since a state written to thecell will be retained until the cell is reprogrammed.

DRAMs on the other hand implement a capacitor that is either charged ordischarged to store the on (state 1) or off (state 2) state of a cell.Capacitors discharge over time, however, and DRAMs must therefore beperiodically ‘refreshed’. Also, a bistable latch can generally beswitched between states much faster than the amount of time it takes tocharge or discharge a capacitor. Accordingly, SRAMs are a desirable typeof memory for certain types of applications including portable devicessuch as laptop computers and personal digital assistants (PDAs).

SRAM is typically arranged as a matrix of thousands of individual memorycells fabricated in an integrated circuit chip, and address decoding inthe chip allows access to each cell for read/write functions. SRAMmemory cells use active feedback from cross-coupled inverters in theform of a latch to store or “latch” a bit of information. These SRAMmemory cells are often arranged in rows and columns so that blocks ofdata such as words or bytes can be written or read simultaneously.Standard SRAM memory cells have many variations.

The basic CMOS SRAM cell generally includes two n-type or n-channel(nMOS) pull-down or drive transistors and two p-type (pMOS) pull-up orload transistors in a cross-coupled inverter configuration, which act asa bistable latch circuit, with two additional nMOS select or pass-gatetransistors added to make up a six-transistor cell (a 6T cell).Additionally, application specific SRAM cells can include an evengreater number of transistors. A plurality of transistors are utilizedin SRAM requiring matched electrical characteristics to providepredictable cell switching characteristics, reliable circuitperformance, and minimize array power dissipation.

Each inverter of the SRAM memory cell includes a load transistor and adriver transistor. The output of the two inverters provide oppositestates of the latch, except during transitions form one state toanother. The pass-gate transistors provide access to the cross-coupledinverters during a read operation (READ) or write operation (WRITE). Thegate inputs of the pass transistors are typically connected in common toa word line (wordline or WL). The drain of one pass transistor isconnected to a bit line (bitline or BL), while the drain of the otherpass transistor is connected to the logical complement of the bit line(bitline-bar or BLB).

A WRITE to a 6T cell is effected by asserting a desired value on the BLand a complement of that value on BLB, and asserting the WL. Thus, theprior state of the cross-coupled inverters is overwritten with a currentvalue. A READ is effected by initially precharging both bitlines to alogical high state and then asserting the WL. In this case, the outputof one of the inverters in the SRAM cell will pull one bitline lowerthan its precharged value. A sense amplifier detects the differentialvoltage on the bitlines to produce a logical “one” or “zero,” dependingon the internally stored state of the SRAM cell.

Accordingly, a consideration in the design of the transistors in theSRAM cell is the geometric parameters of the transistors. The gatelength and width determine in large part the speed and saturation drivecurrent, I_(Dsat), also known as the maximum drive current capacity ofthe transistors. Appropriate values of gate length and width of the sixtransistors of the 6T cell must be chosen to ensure that a readoperation does not destroy the previously stored datum. Inappropriatetransistor parameter values in conjunction with the BL and WL voltagesapplied during a READ may result in a change in state of the memory celldue to random asymmetries resulting from imperfections in themanufacturing process. The necessity to guard against such READinstability places an undesirable constraint on the design parameters ofthe transistors in the 6T cell, limiting the ability of the designer toincrease READ performance of the SRAM while keeping within area andpower constraints and maintaining the ability to write into the cell.

As transistor scaling trends continue, however, it becomes increasinglydifficult to design an SRAM cell that has both adequate static noisemargin (SNM) and adequate trip voltage (Vtrip), because of theirinterdependency in cell design. For example, a design constraint of a 6TSRAM cell is that the pass gate is generally designed to be relativelyweaker than the inverter driver transistor to ensure stability andadequate SNM, yet is also designed to be stronger than the inverter loadtransistor to enable a WRITE by providing adequate Vtrip. Also, forstability, the inverter load transistor cannot be too weak relative tothe inverter driver transistor or SNM is degraded. Inverter transistorswith relatively low threshold voltage (Vt), the voltage at which thetransistor begins to conduct, may also degrade stability of the SRAMcell.

With technology scaling to the 45 nm node and beyond, it may no longerbe possible to achieve this balance in the relative strengths of thepass gate, drive, and load transistors over the desired range oftemperature and bias conditions as well as process variations. Thus, thecurrent balance in these design values often involves a trade-off thatmay translate to a higher incidence of data upsets and/or slower accesstimes.

Prior art includes methods to assist the WRITE to allow the relativelyweaker pass gate for good stability. This prior art includes pulling theBL below the SRAM low voltage supply, V_(SS), for WRITE, or providing alower SRAM high voltage supply, V_(DD), to the inverters for WRITErelative to that for READ. However, the relatively weaker pass gateenabled by this prior art has the undesirable affect of degrading theread current.

Prior art also includes memory cells with separate ports for READ andWRITE that might at first seem to relax some of the constraints to allowa fast READ. However, such cells are generally relatively large. Alsothere is still the constraint of not upsetting the unaddressed cells ina selected row for WRITE in an array in which only a subset of the cellsin a selected row are written into in a single WRITE cycle. The cells inthe selected row that are not written into are subjected to biasconditions similar to that for a READ, and are subject to upset.

Accordingly, there is a need for an improved SRAM cell design thatenables independent optimization of the static noise margin, tripvoltage, and read current of higher speed SRAM cells, while minimizingdata upsets in SRAM memory devices with a relatively compact layout.

SUMMARY

The following presents a simplified summary in order to provide a basicunderstanding of one or more aspects of the invention. This summary isnot an extensive overview of the invention, and is neither intended toidentify key or critical elements of the invention, nor to delineate thescope thereof. Rather, the primary purpose of the summary is to presentsome concepts of the invention in a simplified form as a prelude to themore detailed description that is presented later. The invention relatesto an SRAM memory cell structure (e.g., an 8T single ended and a 10Tdifferential SRAM memory cell) utilizing a read buffer circuit or readcircuit comprising a read transistor for cell selection and coupling toa read bit line when gated by a read word line, and a read drivertransistor that is gated by an output of a cell core for removing orisolating the read current from the latch nodes of the cell during readoperations. Beneficially, the read buffer permits a higher read currentisolated from the latch nodes of the cell during read operations whilepermitting a lower write voltage that avoid upsets to the cell duringwrite operations.

The read buffer circuit is configured to permit a dedicated read wordline (RWL) for read operations and a separate write word line (WWL) foraccessing the core cell during write operations. Accordingly, theindependent read and write word lines permit different voltages on theread word line RWL and write word line WWL for optimizing read currentwhile avoiding data upsets. For example, a relatively higher voltage maybe used on the RWL to obtain more read current, and a relatively lowervoltage on the WWL to avoid upsets.

In one aspect of the invention, the RWL voltage may be boosted above Vddduring read operations while the WWL voltage is kept at Vss or 0 volts.During write operations, the WWL voltage may be switched to Vdd whilethe RWL voltage is kept at Vss or 0 volts.

In another aspect of the invention, the RWL voltage may be driven to Vddduring read operations while the WWL voltage is kept at Vss or 0 volts.During write operations, the WWL voltage may be kept below Vdd while theRWL voltage is kept at Vss or 0 volts.

In still another aspect of the invention, the RWL voltage during readoperations may be the same as the WWL voltage during write operations.

In yet another aspect of the invention, the array Vss is raised toenable the write operation with a lower WWL voltage during writeoperations, while the RWL voltage is boosted during read operations tocompensate for the impact of raised Vss on the read current, using a Vssclamp diode connected between a source terminal of the core cells of thearray (Vss-array) and a source voltage (Vss).

The SRAM memory cell structure of the present invention allowsindependent optimization of the static noise margin, trip voltage, andread current, thereby avoiding some of the static noise margin and tripvoltage problems of conventional SRAM cells (e.g., a conventional 6Tdifferential cell). The structures described herein are applicable tosilicon wafer fabrication and other such fabrication processes in themanufacture of semiconductor memory devices.

In one aspect of the invention, the SRAM cell comprises a differentialcore cell, comprising first and second cross-coupled inverters, thefirst inverter having a first latch node and the second inverter havinga second latch node. This inverter arrangement forms a latch used as thebasic data storage cell, which includes two complementary ordifferential latch nodes. The SRAM cell of the present invention mayfurther be configured having differential read buffers that provide adifferential read mode. The differential read buffer configurationcomprises a read buffer and a complementary read buffer, each bufferhaving a read transistor and a read driver transistor connected to andgated by the opposite latch node of the cell. The read driver transistorand the read transistor of each read buffer are series connected betweena source voltage (Vss) at the source terminal of a read driver and arespective read bitline (RBL) or a complementary read bitline (readbitline bar, RBLB) at the drain terminal of the respective readtransistor. The read and complementary read transistors are connected toa read wordline (RWL) for row (Y) access to the cell during readoperations. The write transistors of the core cell are connected to arow (Y) decoder for access to the cells of a row of cells during writeoperations.

In accordance with still another aspect of the invention, the first andsecond inverters of the SRAM cell comprise a pull-up transistor and apull-down transistor.

In another aspect, the present invention provides for an SRAM cell thathas a pair of cross-coupled inverters, and a write transistor gated by awrite word line (WWL) and coupled between the output of one of thecross-coupled inverters and a write bit-line (WBL). The SRAM cell alsohas a read transistor gated by a read word line (RWL) and coupledbetween a read bit-line (RBL) and a read driver transistor. The readdriver transistor is coupled between the read transistor and a sourcevoltage, and is gated by an output of one of the cross-coupledinverters.

In one aspect of the invention, the read buffer circuit comprises a readtransistor that has an electrical characteristic which differs from thatof the transistors used in the core cell.

In another aspect the electrical characteristic of the read transistoris a lower threshold voltage Vt or a shorter gate length.

In still another aspect the electrical characteristic of the readtransistor is a maximum drive current, wherein the read transistor has agreater drive current than the write transistor.

In yet another aspect, the present invention provides an SRAM device,including an array of SRAM cells arranged in rows and columns. A writeword line (WWL) is associated with at least one row for writeoperations, and is operable to control access to cells in the row forwrite operations. A write bit-line (WBL) is associated with at least onecolumn, and is operable to provide input to the cells in the column fora write. A read word line (RWL) is associated with at least one row, andis operable to control access to cells in the row for read operations. Aread bit-line (RBL) is associated with the column operable to receiveoutput from cells in the column.

During the read operation of a conventional 6T SRAM cell, a read currentis passed through a latch node of the selected data storage cell. Theread current produces a voltage drop (Vdrop) across the associatedpull-down transistor of the cell. This voltage drop requires thepull-down transistors to have a sufficiently high enough thresholdvoltage (Vt) to remain in the off-state during a read operation. Thus,measures to increase the read current of a conventional 6T SRAM cellwithout increasing area, such as reducing Vt or increasing the currentcapacity of the pass gate, tend to reduce cell stability.

Accordingly, a goal of the present invention is to provide a readcurrent, which is indicative of the data state of the cell, yet removedfrom loading the data nodes or latch nodes of the cell. In accordancewith the present invention, this goal is accomplished by adding a readbuffer (e.g., a transistor, or another such read buffering circuit)outboard from the data cell that passes the read current. The controlterminal (e.g., gate) of the read driver is connected to the oppositedifferential latch node of the cell. For example, the gate of a readdriver transistor may be connected to the same node as the gate of theassociated pull-down transistor of the SRAM cell.

Further, during a write operation of a conventional 6T SRAM cell, thewordline is asserted to all the cells associated with the selectedwordline, including those cells that are not in selected columns. Inparticular, these unselected data bits reside along the selectedwordline, but are in the other unselected columns of the array. As theselected cell or cells are written into, the data in the unselectedcells along the selected wordline may be upset, and in addition mayconsume unnecessary supply power charging the unselected cells.Accordingly, a goal of the present invention is to permit concurrentoptimization of the read current and stability of cells during WRITE, byproviding a read pass gate transistor or read transistor gated by a readword line (RWL) for use during a read operation.

To the accomplishment of the foregoing and related ends, the followingdescription and annexed drawings set forth in detail certainillustrative aspects and implementations of the invention. These areindicative of but a few of the various ways in which the principles ofthe invention may be employed. Other aspects, advantages and novelfeatures of the invention will become apparent from the followingdetailed description of the invention when considered in conjunctionwith the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic diagram of a conventional 6T static random accessmemory (SRAM) cell and SRAM core cell having a pair of output datanodes;

FIG. 1B is a simplified schematic diagram of the conventional 6T staticrandom access memory (SRAM) cell of FIG. 1A, with the core cellrepresented as a pair of cross-coupled inverters connected to the outputdata nodes;

FIG. 2A is a schematic diagram of a single sided 8T SRAM cell having aread buffer to isolate the read current from a data node of the 6T SRAMcell of FIG. 1A during a read operation according to one or more aspectsof the present invention;

FIG. 2B is a schematic diagram of a single sided 9T SRAM cell similar tothat of FIG. 2A, further comprising a Vss clamp diode connected betweena source terminal of the core cell and a source voltage (Vss), wherebythe array Vss is raised to avoid degrading a lower WWL voltage duringwrite operations, while the RWL voltage is boosted during readoperations to compensate for the impact of raised Vss on the readcurrent according to one or more aspects of the present invention;

FIG. 2C is a schematic diagram of a differential 10T SRAM cell, similarto the SRAM cell of FIG. 2A, having a complementary pair of read buffersto isolate the read current from the data nodes of the 6T SRAM cell ofFIG. 1A during a read operation according to one or more aspects of thepresent invention;

FIG. 2D is a schematic diagram of an exemplary array of memory cells,similar to the SRAM memory cell of FIG. 2A, the array having columns ofread and write bitlines and rows of read and write wordlines accordingto one or more aspects of the present invention;

FIG. 2E is a schematic diagram of an exemplary array of memory cells,similar to the SRAM memory cell of FIG. 2B, the array having columns ofread and write bitlines, rows of read and write wordlines, and a Vsssupply circuit according to one or more aspects of the presentinvention;

FIGS. 3A, 3B, and 3C are simplified plots of several exemplary readwordline RWL and write wordline WWL voltages which may be used in theSRAM memory cells of FIGS. 2A and 2C during idle, read, and writeoperations according to one or more aspects of the present invention;

FIGS. 4-7 are plan views of exemplary physical layouts of transistors inan 8T SRAM cell such as that of FIG. 2A having 3 bitlines (BL) and 2wordlines (WL), designed in accordance with the principles of thepresent invention;

FIG. 8 is a plan view of an exemplary physical layout of transistors inan 10T SRAM cell such as that of FIG. 2C having 4 bitlines (BL) and 2wordlines (WL), designed in accordance with the principles of thepresent invention;

FIG. 9A is a schematic diagram of an alternate embodiment of a singlesided 8T SRAM cell, having a read buffer to isolate the read currentfrom a data node of the 6T SRAM cell similar to that of FIG. 1A during aread operation, wherein the read transistor of the read buffer and thewrite transistor of the core cell share a common word line, according toanother aspect of the present invention;

FIG. 9B is a schematic diagram of an alternate embodiment of a singlesided 9T SRAM cell, similar to the 8T SRAM cell of FIG. 9A, furthercomprising a Vss clamp diode connected between a source terminal of thecore cell and a source voltage (Vss), according to one or more aspectsof the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

The present invention will now be described with reference to theattached drawings, wherein like reference numerals are used to refer tolike elements throughout. The invention provides an SRAM memory cellstructure (e.g., an 8T single ended and a 10T differential SRAM memorycell) utilizing a read buffer circuit for removing or isolating the readcurrent from the latch nodes (data nodes) of the core cell or data cellduring read operations, provides a separate read word line for selectionof cell columns or a single cell during read operations, and provides aseparate write word lines for selection of cell columns or a single cellduring write operations.

Because the read current is isolated from the data storage cell of thepresent invention, the read drive current or maximum drive currentthrough the read buffer may be increased over that which is often usedin the write transistors of a conventional 6T differential cell.Further, the threshold voltage Vt used in the transistors of the readbuffer may be lower than that used in the transistors of the core cell.Finally, the static noise margin (SNM), trip voltage (Vtrip), and readcurrent (Iread) may be independently optimized, thereby avoiding some ofthe static noise margin and trip voltage compromises and problems ofconventional SRAM cells (e.g., a conventional 6T differential cell).

The read buffer circuit of the present invention comprises a readtransistor for selectively coupling a read current to a read bit line,RBL, associated with a column (X) of cells, when gated by a read wordline RWL, and a read driver transistor that is gated by a latch node(output) of a cell core for modulating the read current according to thestate of the cell.

With scaling, it is increasingly difficult to balance the requirementsfor being able to write into a cell without causing an upset of thecell. The read and write functions can be separated by adding a readbuffer, but it is still necessary to be able to write without upsetbecause of interleaving (having unaddressed columns in an addressedrow). The ability to write without upset, leads to trade-offs in areaand in read speed. It is possible to avoid upsets by using somecombination of lower WL voltage, high Vt, and a write access transistorthat is weaker than the cell driver transistor. However, such methods toavoid upsets tend to degrade performance (slower read due to low readcurrent) and make the write more difficult. The difficulty in write canbe overcome by write assist circuits, such as driving the write BL lowerrelative to the array VSS, however, this still leaves the performancelow.

One aspect of the invention is to have a read buffer and to design thecore 6T with transistor sizes, threshold voltages, and WL voltages thatallow write without upset, but this would reduce the read current. Theread buffer could then be designed with transistors that have differentcharacteristics compared to the core 6T transistors to improve readcurrent. Thus, the present invention not only addresses having the readdriver transistor different from the core inverter driver transistor,but also includes having the read transistor different from the writetransistor to avoid cell upsets and other advantages discussed herein.

Alternatively, the read WL may be separate from the write WL and ahigher voltage may be used for the read operation.

Thus, the present invention contemplates both designing the core 6T toavoid upsets using a read buffer having transistors characteristics thatare different from the transistors in the core 6T so as to improveIread, and by using a lower voltage for the write WL relative to theread WL enhanced by write assist circuits. That is, the write assistcircuits enable the write with the higher Vt's or the lower WL voltage.

As indicated previously, feature scaling trends continue down to around45 nm areas or less, it may no longer be possible to achieve a balancein the relative strengths of the pass gate, drive, and load transistorsover the desired range of temperature and bias conditions as well asprocess variations.

The inventors of the present invention have realized that the readcurrent produces a voltage drop (Vdrop) across the associated pull-downtransistor and latch node of the conventional cell, thereby raising thevoltage of the respective latch node. This voltage drop requires thepull-down transistors to have a sufficiently high enough thresholdvoltage (Vt) to remain in the current data state during a readoperation. As a result, the effective static noise margin (SNM) whichremains (between the Vt and the Vdrop) is reduced and the data state ofthe selected cell may be more unstable. Accordingly, the inventorsrealized that the stability of the cell may be increased by removing orisolating the read current from the data cell using a read buffer (e.g.,a transistor, or another such read buffering circuit). The read bufferof the present invention responds to the data state of the cell, butdoes not reflect the read current or the read current induced voltagedrop back into the SRAM core cell or the opposite latch node which gatesthe read driver transistor of the read buffer. As a result, theinterdependence between the SNM and the read current is removed from thedata cell.

Further, the present invention avoids upsetting the unaddressed cellsalong an addressed wordline during a WRITE, by providing a relativelylower wordline voltage to the dedicated write word line WWL connected tothe write pass gate or write transistors of a conventional 6T core cell.In addition, this arrangement may be useful to limit power dissipationin the array to the cell or cells that are accessed. Therefore, arelatively higher voltage may be used on the RWL to obtain more readcurrent during READ operations, and a relatively lower voltage may beused on the WWL to avoid upsets during WRITE operations.

The inventors have also realized that the sizes and threshold voltagesof the transistors of the core cell, the pass gates, and the read buffermay then be optimized. For example, to decrease the access time, theread current may be increased by increasing the size of the readtransistor on the read word line RWL relative to that of the writetransistors on the write word line WWL or the core driver transistorswithin the core cell.

Exemplary implementations are hereinafter illustrated and described inthe context of fabricating SRAM cell structures to permit a highervoltage on the read word line RWL and to remove the interdependencebetween the SNM and the Vtrip of the conventional 6T SRAM cell in orderto improve the optimization of a cell, and to avoid read and write dataupsets, wherein the structures illustrated are not necessarily drawn toscale. It will be appreciated that the invention may be employed in thefabrication of SRAM memory devices, silicon wafer fabrication and othersuch fabrication processes in the manufacture of semiconductor memorydevices, and other such processes apart from the exemplary memorystructures described and illustrated herein. These and other benefitswill become more apparent as the following figures are described infra.

Beginning at FIGS. 1A and 1B a conventional 6T SRAM cell 1 isillustrated and several problems arising from read operations arepresented.

FIG. 1A, for example, illustrates a schematic diagram for theconventional differential 6T static random access memory (SRAM) cell 1.SRAM cell 1 comprises a data storage cell, latch, or core cell 2,generally including a pair of cross-coupled inverters, for example,inverter 12, and inverter 14, the latch 2 operable to store a data bitstate. As illustrated in FIG. 1A, the bit is stored in the latch 2 atthe data nodes or first and second latch nodes 4 and 6, respectively,having a high or “1” state and a low or “0” state, respectively. Cell 1also comprises a pair of wordline pass transistors 16, 18 to read andwrite the data bit between the cross-coupled inverters 12, 14 andbitlines BL 30, BL-bar 31, when enabled by wordline 32.

Respective inverters 12, 14 comprise a p-type MOS (pMOS) pull-up or loadtransistor Q1 20, Q2 22 and an n-type (nMOS) pull-down transistor Q3 24,Q4 26. Pass transistors Q5 16, Q6 18 are n-channel as well, whichgenerally supply higher conductance than p-channel transistors. Passtransistors 16, 18 are enabled by wordline 32 and accessed by bitlines30, 31 to set or reset the SRAM latch 1. FIG. 1A further illustratesthat inverters 12, 14 of the SRAM memory cell 1 are connected togetherto a Vdd drain voltage line 40 and a Vss source voltage line 50.

The differential 6T SRAM cell comprises six transistors and is termed a6T full CMOS SRAM cell. When the channels of all the transistors areformed in the single crystal silicon substrate, it is called a singlecrystalline bulk CMOS 6T SRAM cell. It is also referred to as a planarSRAM cell when all the transistors are made in the same substratematerial (e.g., bulk crystalline silicon, SOI, etc.).

In general, SRAM cells are more stable and have better data retentionwhere the respective pMOS (20, 22) and nMOS (24, 26) transistors areload balanced and matched for the two inverters (12, 14). However, asdimensions are reduced to scale down devices, random variation increasesand it becomes increasingly difficult to achieve a balance in therelative strengths of the pass gate, drive, and load transistors overthe desired range of temperature, bias conditions, and processvariations in the presence of the range of random variation that occursover the large number of cells in an array. As a result, SRAM cellsformed as such can be adversely affected by varying operatingcharacteristics, may be unstable, and may not retain the desired bitstate during read or write operations, or data may not be reliablywritten into the cells, or there may be insufficient read current.

During the read operation, for example, bitlines 30 and 31 areprecharged to a high or “1” state, as shown in FIG. 1A. Wordline WL 32is selected to activate pass transistors Q5 16 and Q6 18 intoconduction. As a high state at latch node 4 is on the gate of Q4 26, anda low state at latch node 6 is on the gate of Q3 24, only Q4 26 on the“low side” conducts a read current 64. Read current Iread 64, conductsfrom the bitline-bar 31 through Q6 18, latch node 6, and Q4 26 to Vss50. The read current 64 through Q6 and Q4 briefly creates a voltage dropVdrop 66 across Q4 26, until the voltage on bitline-bar 31 is dischargedto Vss 50 (e.g., ground). If sufficient voltage drop 66 is created byread current 64 to raise latch node 6 to the threshold voltage Vt of Q324, then Q3 may begin conducting and the data state of latch 2 may beupset.

Thus the relative relationship between the voltage drop Vdrop 66 acrosspull-down transistor Q4 26 during a read operation, the static noisemargin SNM, and the threshold voltage Vt of the n-channel pull-downtransistors (VTnch) Q3 24, and Q4 26 of SRAM memory cell 1 of FIG. 1A.The SNM reflects the statistical data loss due to read upsets. Forexample, if SNM is too low, some bits of an array of cells will start tofail in a Gaussian distribution. Thus during a read operation, thegreater the voltage drop Vdrop 66 across the pull-down transistor, thesmaller will be the remaining static noise margin SNM within theavailable threshold voltage VTnch. Therefore, it is desirable to lowerthe voltage drop Vdrop 66, or better still to avoid its affect on thelatch nodes 4 and 6 in order to maximize the SNM and optimize theswitching characteristics of the latch 2.

FIG. 1B illustrates the conventional 6T static random access memory(SRAM) cell 1 of FIG. 1A, with the data storage cell, latch, or corecell 2 represented as a pair of cross-coupled inverters 12 and 14 havingthe output data nodes 4 and 6, respectively.

FIG. 2A illustrates an exemplary eight-transistor (8T) SRAM cell 200comprising a 6T SRAM cell 101 having a core cell 102, the 8T SRAM cell200 modified from that of the conventional 6T SRAM cell 1 of FIG. 1A,using a read buffer 204 to remove the read current from latch nodes 104and 106 of the cell 101 according to one or more aspects of the presentinvention. The read buffer 204 further comprises a read transistor Q7207 (acting as a read pass gate) and a read driver transistor Q8 208series connected between a read bitline RBL 234 and a source voltage Vss150. The read transistor Q7 207 is gated by a read word line RWL 236 toaccess the data state of cell 102 by way of the conduction state of Q8208 to bitline RBL 234. The read driver transistor Q8 208 also has agate connected to the gate of the n-channel pull-down transistor Q4 126and the latch node 104. Clearly, in this arrangement, read driver Q8 208will therefore reflect the conduction of Q4 126, and thus produce a readcurrent that mirrors transistor Q4 126 as described below.

The exemplary 8T SRAM cell 200 of FIG. 2A comprises three bitlines(e.g., write bitline WBL 130, write bitline bar WBLB 131, and readbitline RBL 234) and two wordlines (e.g., write word line WWL 132, andread word line RWL 236) or (3BL/2WL).

During a read operation of cell 200, the read bitline RBL 234 isprecharged to a high or “1” state, as shown in FIG. 2A. Read word lineRWL 236 is selected to activate read transistor Q7 207 into conduction.For example, with the prior data states as shown in FIG. 2A, anexemplary read current Iread 64, conducts from the read bitline RBL 234through read transistor Q7 207, and read driver Q8 208 to Vss 150.

Again, the read current Iread 64 through Q7 and Q8 briefly creates avoltage drop Vdrop 66 across Q8 208, until the charge on read bitlineRBL 234 is discharged to Vss 150. However, with this configuration ofthe present invention, the read current Iread 64 beneficially bypassesQ4 126 and the latch node 106, thereby avoiding a voltage drop across Q4126 and a possible data upset therefrom. Although a voltage drop Vdrop66 is still produced across Q8 208, this voltage has no path to becoupled back to the latch node 106 of the cell 101 as in theconventional 6T SRAM configuration. Thus, Q7, Q8, and RWL voltage can beoptimized for high read current without concern for cell stability,while Q3, Q4, Q5, Q6, and WWL voltage can be optimized for SNM and writewithout concern for read current. The 8T cell of FIG. 2A illustrates thebasic read operation concept of the 8T SRAM cell of the presentinvention.

FIG. 2A may also be described and represented in another manner, whereinan eight-transistor (8T) SRAM cell 200 comprises an SRAM cell core 102,and circuitry for writing to and reading from the SRAM cell core,according to the principles of the present invention. SRAM cell core 102is a conventional design using two inverters. A first inverter 112comprises a first driver transistor 124 and a first load transistor 120.A second inverter 114 comprises a second driver transistor 126 and asecond load transistor 122. In this conventional embodiment of SRAM cellcore 102, the driver transistors 124 and 126 are n-channel MOSFETs, andthe load transistors 120 and 122 are p-channel MOSFETs.

The first inverter 112 has a first output 104 formed by a connectionbetween the drain of the first load transistor 120 and the drain of thefirst driver transistor 124, and a first input 106 formed by aconnection between the gate of the first driver transistor 124 and thegate of the first load transistor 120. Similarly, the second inverter114 has a second output 106 formed by a connection between the drain ofthe second load transistor 122 and the drain of the second drivertransistor 126, and a second input (or the first output) 104 formed by aconnection between the gate of the second load transistor 122 and thegate of the second driver transistor 126. In a conventional manner, thefirst and second inverters 112, 114 are cross-coupled, meaning that theoutput of each inverter is connected to the input of the other, to forman SRAM cell core that stores a single bit of information.

Also in a conventional manner, a write transistor 118 is connected tothe first output 104. Similarly, a complementary write transistor 116 isconnected to the second output 106. The gates of write transistor 118and complementary write transistor 116 are each connected to a writewordline (WWL) 132. Together, the write transistor 118 and thecomplementary write transistor 116 form a write circuit that is used toimpose a state on the SRAM cell 200 in cooperation with the WWL 132, awrite bit-line (WBL) 130 and a complementary write bit-line (WBLB) 131.For example, if the WBL 130 is set to a value of Vdd 140 while the WBLB131 is set to value of Vss 150, then, when the WWL 132 is asserted (setto Vdd), the output of the first inverter 112 will be set to a value ofVdd plus the drain-source voltage of load transistor 120, while theoutput of the second inverter 114 will be set to Vss plus thedrain-source voltage of driver transistor 126. This state may beinterpreted as a logical “one” for the SRAM cell core 102. It isimmediately apparent that repeating this operation with the WBL 130 setto Vss and the WBLB 131 set to Vdd would result in setting the SRAM corecell 102 to a logical “zero.”

In one embodiment of the invention, a state of the SRAM cell core 102can be determined by using a read circuit 204 including a readtransistor 207 and a read driver transistor 208. In the embodiment shownin FIG. 1, the gate of the read driver transistor 208 is connected tothe first output 104 of the first inverter 112. A source of the readtransistor 207 is connected to a drain of the read driver transistor208, and a drain of the read transistor 207 is connected to a readbitline (RBL) 234. The gate of the read transistor 207 is connected tothe read word line (RWL) 236, while the gate of the write transistors116 and 118 are connected to the write word line (WWL) 132, thus thewrite transistors 116, 118 and the read transistor 207 are controlled byseparate word line selection signals. The use of individual word linesfor the READ and WRITE operations permits customized READ and WRITEoperation voltages that avoids a trade-off between a fast (highervoltage, higher current) read access and a stable write (lower voltagewrite) that avoids data upsets in a memory device comprising SRAM cell200, while permitting a compact cell layout.

When the SRAM cell core 102 is storing a logical zero, the output of thesecond inverter 114 is high, thereby turning on the read drivertransistor 208, and forming a low resistance path from the drain of theread driver transistor 208 to Vss 150. The state of the SRAM cell 200may be determined by precharging the state of the RBL 234 toapproximately Vdd and asserting the RWL 236. Alternatively, the RBL 234may be precharged to a voltage lower than Vdd to reduce power consumedby the READ. Because the read driver transistor 208 is on, when the readtransistor 207 is turned on by asserting the RWL 236, the RBL 234 ispulled below its precharge voltage. However, if the SRAM cell 200 is setto a logical one, then the output of the second inverter is a logicalzero, and the read driver transistor 208 will be off. When the RWL 236is asserted, the read transistor 207 is turned on, but the RBL 234remains at the precharge voltage, or logical one.

Those skilled in the art of SRAM cell design will appreciate that theelectrical characteristics of the inverter transistors and writetransistors are balanced to optimize the stability of the SRAM cell 200.If both read and write functions were provided by the write transistor118 and the complementary write transistor 116, the time required for aread operation would be constrained by the maximum drive current(IDsat), and turn-on time of the write transistor 118 and thecomplementary write transistor 116. However, the present inventionadvantageously allows the maximum drive current or threshold voltage ofthe read transistor 207 to be designed substantially independently ofthe constraints on SRAM cell stability. Thus, the read transistor 207can be designed with different electrical characteristics than the writetransistor 118 or either of the driver transistors 124, 126 of the corecell 102.

In one embodiment, the read transistor 207 is designed to have a largerIDsat than the write transistor 118, or alternately of any of the othertransistors of the core cell 102. In an alternate embodiment, the readtransistor 207 is designed to turn on faster than does the writetransistor 118. In yet another embodiment, the threshold voltage of readtransistor 207 is designed to be lower than the threshold voltage ofwrite transistor 118, or alternately of any of the other transistors ofthe core cell 102. One skilled in the art will appreciate that theseembodiments can be combined as desired to result in the desired SRAMperformance.

Those skilled in the pertinent art will also appreciate that in anotheralternate embodiment, the read circuitry could be designed usingcomplementary transistor polarity. For example, the read transistor 207could be a p-channel transistor. In this embodiment, the drain of theread transistor 207 is connected to the drain of the read drivertransistor 208, and the source of the read transistor 207 is connectedto the RBL 234. The RWL 236 is then asserted as a logical zero, therebyturning on read transistor 207 during a READ. In another embodiment,read driver transistor 208 is also implemented as a p-channeltransistor, with its source connected to Vdd 140. In this embodiment,the RBL 234 is precharged low, and pulled up to a logical one when a lowvoltage at the second inverter output 140 turns on the read drivertransistor 208 (thereby making the read driver transistor 208 a pull-uptransistor).

FIG. 2B illustrates an exemplary single sided 9T SRAM cell 250 similarto that of FIG. 2A according to one or more aspects of the presentinvention. Cell 250 comprises a further modification of the 8T SRAM cellof FIG. 2A, and therefore need not be completely described again for thesake of brevity. 8T SRAM cell 250 comprises a latch 102 that uses theread buffer having read driver transistor Q8 208 and read transistor Q7207 to remove the read current (e.g., Iread 264) from the first orsecond data nodes 104 and 106, respectively, during a read operation.Cell 250 further adds a transistor Q9 219 connected as a diode between asource terminal (e.g., Vss-Array 255) of the core or data cell 102 and asource voltage Vss 150. Transistor Q9 219 may be shared among the many8T cells 250 in an SRAM array, such as array 290 of FIG. 2E that will bediscussed further infra More generally, a VSSA voltage is supplied tothe array, where VSSA is >Vss of the periphery, or, more particularly,greater than the Vss of the write BL driver. In this embodiment of thepresent invention, the array-Vss 255 may be raised in conjunction with arelatively low write word line voltage 132 to enable a WRITE withoutupset of the cells in unaddressed columns. This is one embodiment of awrite assist that enables the cell to be written with a WL voltage thatis below a level that would cause an upset of cells in unaddressedcolumns of the addressed row. Those familiar with the art of memorydesign will realize there are other write assist circuits, such as useof capacitive coupling to drive a write bit line negative relative toVSSA, or selectively lowering VDD to the addressed columns. For readoperations, the read wordline may be high relative to the write WLvoltage to compensate for the impact of a raised Vss (e.g., Vss-Array255) on the read current (e.g., Iread 264).

For example, the Vss is raised to VSSA by a Vss supply circuit 256, suchas by Q9 219 used as a clamp diode. Alternately, a Vss supply circuit256, such as transistor Q9 219 may be included in every SRAM memory cell250 of the array as is illustrated in array 280 of FIG. 2D.

The exemplary 8T SRAM cell 250 embodiment of FIG. 2B comprises threebitlines (e.g., write bitline WBL 130, write bitline bar WBLB 131, andread bitline RBL 234) and two wordlines (e.g., write word line WWL 132,and read word line RWL 236) or (3BL/2WL).

FIG. 2C is a schematic diagram of a differential 10T SRAM cell, similarto the SRAM cell of FIG. 2A, having a complementary pair of read buffers(e.g., first read buffer 204 and second read buffer 205), to isolate theread current from both the data nodes of the 6T SRAM cell 101 of FIG. 2Aduring a read operation according to one or more aspects of the presentinvention.

10T SRAM cell 270 comprises a further modification of the 8T SRAM cellof FIG. 2A and therefore need not be completely described again for thesake of brevity. 10T SRAM cell 270 comprises a read buffer on each sideof a latch 102, each read buffer 204, 205 having read driver transistorQ8 208 and read transistor Q7 207 to remove the read current (e.g.,Iread 264) from the first and second data nodes 104 and 106,respectively, during a read operation. The exemplary 10T SRAM cell 270embodiment of FIG. 2C comprises four bitlines (e.g., write bitline WBL130, write bitline bar WBLB 131, read bitline RBL 234, and complementaryread bitline bar RBLB 235) and two wordlines (e.g., write word line WWL132, and read word line RWL 236) or (4BL/2WL).

Cell 270 comprises read transistors Q7 207 and Q9 229, respectively toselect a row of cells during a read operation. Initially, columns ofcells may be activated by selecting and precharging read bitlines RBL234 and RBLB 235 (e.g., asserting a bitline selection signal or voltage)associated with cell 270, either before or during a read or writeoperation, such that the cell 270 is selected and activated. Thereafter,the rows are selected during a read operation by asserting read wordlineRWL 236 to the gates of read transistors Q7 207 and Q9 229,respectively, to couple first and second latch nodes 104 and 106 to RBL234 and RBLB 235, respectively.

During the read operation, read bitlines RBL 234 and RBLB 235 of cell270, are precharged to a high or “1” state. Read wordline RWL 236 isselected (e.g. by asserting a read signal or voltage) to activate readtransistors Q7 207 and Q9 229 into conduction, and the write word lineWWL 132 is deselected, turning off Q5 116 and Q6 118. For example, withthe prior data states shown in FIG. 2A, an exemplary read current Iread264 conducts from the RBL 234 through read transistor Q7 207, and readdriver Q8 208 to Vss 150. For improved conduction to the latch 102, theread signals to read transistors Q7 207 and Q9 229, may be boosted abovethe Vdd supply voltage level, as will be discussed further in connectionwith FIGS. 3A-C infra.

Again, a read current Iread 264 through Q7 and Q8 briefly creates avoltage drop Vdrop 266 across Q8 208, until the charge on RBL 234 isdischarged to Vss 150. However, with this configuration as with that ofFIG. 2A, the read current Iread 264 beneficially bypasses pull-downtransistors Q3 124 or Q4 126 and the latch nodes 104 or 106,respectively, thereby avoiding a voltage drop across Q3 124 or Q4 126and a possible data upset therefrom. The voltage drop Vdrop 266 is stillproduced across Q8 208, however, this voltage is not coupled to thelatch node 106 of the cell as a read from BL 30 was in the conventional6T SRAM configuration of FIG. 1A. Thus, the 10T cell of FIG. 2Cillustrates that the read current Iread 264 is isolated from the latchnodes 104 and 106 of the cell of the present invention.

During a write operation, write wordline 132 is selected (e.g., byasserting a write signal or voltage to the wordline) to the gates ofwrite (pass) transistors Q5 116 and Q6 118. In this way, the latch nodes104 and 106 are conductively coupled to the write bitlines WBL 130 andWBLB 131, respectively, during a write operation. To avoid data upsetsto the latch 102, the write signal on WWL 132 to write transistors Q5116 and Q6 118, may be dropped below the Vdd supply voltage level, aswill be discussed further in connection with FIGS. 3A-C infra.

FIG. 2D illustrates an exemplary array 280 of SRAM memory cells 200,similar to the SRAM memory cell 200 of FIG. 2A according to one or moreaspects of the present invention. The memory cells 200 of array 280 arearranged in rows (e.g., Row 1, . . . , Row n) and columns (e.g., Column1, . . . , Column m) of cells 200. In addition, array 280 has columns(e.g., Column 1, . . . , Column m) of read and write bitlines, forexample, WBL 130, WBLB 131, and RBL 234, respectively, and rows of readand write wordlines (e.g., Row 1, . . . , Row n), for example, WWL 132and RWL 236, respectively. The write bitlines WBL 130 and WBLB 131, aredriven with complementary states by a write bitline driver 282 duringmemory write operations. Thus, it may be observed from FIGS. 2A and 2Dthat the gate of the read transistor Q7 207 is connected to a read wordline RWL 236 associated with a row of cells 200 (e.g., Row 1, . . . ,Row n), wherein the read word line RWL 236 is operable to control accessto the cells 200 in the row during a read operation, and wherein a drainof the read transistor Q7 207 is connected to a read bit line RBL 234associated with a column of cells 200 (e.g., Column 1, . . . , Columnm), wherein the read word line RBL 234 is operable to control access tothe cells 200 in the row during a read operation.

FIG. 2E illustrates an exemplary array 290 of SRAM memory cells 250,similar to the SRAM memory cell 250 of FIG. 2B according to one or moreaspects of the present invention. The array 290 of FIG. 2E is similar tothe array 280 of FIG. 2 d, and as such need not be described again fullyfor the sake of brevity. The memory cells 250 of array 290 are arrangedin rows (e.g., Row 1, . . . , Row n) and columns (e.g., Column 1, . . ., Column m) of cells 250. In addition, array 280 has columns (e.g.,Column 1, . . . , Column m) of read and write bitlines, for example, WBL130, WBLB 131, and RBL 234, respectively, and rows of read and writewordlines (e.g., Row 1, . . . , Row n), for example, WWL 132 and RWL236, respectively. The write bitlines WBL 130 and WBLB 131, are drivenwith complementary states by a write bitline driver 282 during memorywrite operations.

Array 290 further comprises a Vss supply circuit 256, such as the clampdiode Q9 219 of FIG. 2B, for example. When a single Vss supply circuit256 (e.g., a write assist circuit) is utilized for the entire array, theVSSA 255 connection from each of the cells 250 may be connected to thesingle or common Vss supply circuit 256. Alternately, a VSS supplycircuit may be provided for each column or for each row. Alternately,and as discussed previously, it will be appreciated in the context ofthe present invention, that a Vss supply circuit 256 or transistor Q9219 may be included within each memory cell. For example, FIG. 2Eillustrates an exemplary circuit when one Vss supply circuit 256 is usedfor the whole array, however, if the Vss supply circuit 256 is includedwithin each 8T cell to form a 9T cell, for example, then the Vss supplycircuit 256 of FIG. 2E would not be needed, and the line labeled VSSA255 in the schematic would directly connect to Vss 150.

The circuit of array 290 provides conditions where VSS-array (VSSA 255)is >Vss as the write BL driver 282 provides a voltage closer to Vss thanthat of the Vss supply circuit 256, and wherein Vss is applied to thewrite BL driver circuitry 282 driving the write bitlines WBL 130 andWBLB 131. Thus, in the embodiment of the present invention, thearray-Vss 255 may be raised in conjunction with a relatively low writeword line voltage 132 to enable a WRITE without upset of cells inunaddressed columns.

FIGS. 3A, 3B, and 3C illustrate several exemplary plot combinations ofread wordline RWL 310 and write wordline WWL 320 voltages, which may beused in the SRAM memory cells of FIGS. 2A and 2C, for example, duringidle, read, and write operations according to one or more aspects of thepresent invention. Plots 300, 325, and 350 illustrate the appliedwordline voltage “V” on the vertical (X) axis, and time “t” on thehorizontal (Y) axis.

Because the SRAM cells of the present invention (e.g., FIGS. 2A and 2C)have independent wordlines, for example, read word lines RWL 236 andwrite wordline WWL 132, these wordlines may have different voltages.Plot 300 of FIG. 3A, for example, illustrates idle, read, and writeoperations having the same read wordline voltage RWL 310 during a readoperation as the write wordline WWL 320 voltage during a writeoperation. In the example of FIG. 3A, RWL 310 and WWL 320 are bothdriven to Vdd during their respective operations.

Plot 325 of FIG. 3B illustrates idle, read, and write operations havinga different read wordline voltage RWL 310 during a read operation ascompared to the write wordline WWL 320 voltage during a write operation.In this example, RWL 310 is boosted above Vdd during a read operationand WWL 320 is driven only to Vdd during the write operation. Thus,boosting the read signals above the Vdd supply voltage level to readtransistors (e.g., Q7 207 and Q9 229) during read operations, willimprove conduction to the latch 102.

Plot 350 of FIG. 3C also illustrates idle, read, and write operationshaving a different read wordline voltage RWL 310 during a read operationas compared to the write wordline WWL 320 voltage during a writeoperation. In this example, RWL 310 is driven only to Vdd during a readoperation and WWL 320 is dropped down below Vdd during the writeoperation. Thus, the write signal WWL 320 to write transistors (e.g., Q5116 and Q6 118) may be dropped below the Vdd supply voltage level duringwrite operations to avoid data upsets to the latch 102.

FIGS. 4-7 illustrate several exemplary physical layouts 400, 402, 404,406, respectively, of transistors in an 8T SRAM cell such as that ofFIG. 2A having 3 bitlines (BL) and 2 wordlines (WL) providing asingle-ended read configuration, designed in accordance with theprinciples of the present invention. FIG. 8 illustrates an exemplaryphysical layout 870, of transistors in a 10T SRAM cell such as that ofFIG. 2C having 4 bitlines (BL) and 2 wordlines (WL) providing adifferential read configuration, designed in accordance with theprinciples of the present invention. Layouts 400, 402, 404, 406, and870, for example, illustrate a read buffer 204 gated by an output of alatch (e.g., latch 102), where the output of the latch is coupled to theread buffer 204 by an extension of the gate of the second driver 126.

Turning now to FIG. 4, for example, an exemplary physical layout 400 ona semiconductor substrate is shown of the SRAM cell 200 with readbuffering and write circuitry shown in FIG. 2A. For clarity, only theactive and gate structures and a schematic indication of theinterconnection of the inverters are shown. The layout of the bit-lines,word lines and power supply lines can follow standard design familiar tothose skilled in the art of SRAM design. The SRAM core cell 102comprises a first driver transistor 124 and a first load transistor 120,and a second driver transistor 126 and a second load transistor 122, aswell as contacts 410 and interconnects 420.

The first driver transistor 124 and a complementary write transistor 116share an n-type active region 430, as do the second driver transistor126 and a write transistor 118. Additionally, a read transistor 207 anda read drive transistor 208 share another n-type active region 430. Thefirst and second load transistors 120 and 122, respectively, are formedwithin independent p-type active regions 440. A p-type active region 440may be common with a p-type active region in an adjacent cell, not shownfor clarity, as would be understood by those familiar with the art. Thegates of the second driver transistor 126, the second load transistor122 and the read drive transistor 208 have a common gate structure,meaning they are coupled using a single strip of gate material, (e.g.,polysilicon). Similarly, the gates of the first driver transistor 124and the first load transistor 120 have a common gate structure. The gatelengths (Y-axis in the Figures) of the gates of the read transistor 207and the read driver transistor 208 are shown to be different as is shownin the layouts of FIGS. 4, 5, 7, and 8 of other embodiments of thepresent invention, although those skilled in the art will recognize thatthese gate lengths could be designed to be the same and remain in thespirit of the present invention.

Alternately, the read transistor gate length may be made longer thansome minimum to reduce leakage to the read bit line, and to have theread driver gate length minimized in order to maximize read current. Inaddition, it is advantageous to have the gate lengths in the core cellto be longer than a minimum length and to have the gate length of theread driver transistor at a minimum gate length. The longer gate lengthgenerally reduces variation and reduces leakage to the core cell whilethe shorter gate length increases read current. Reducing variation andreducing leakage are desirable for the core cell while increased currentdrive is generally unimportant in the core cell. The opposite is thecase for the read driver transistor.

The gate width of the read driver transistor 208 is also shown in theembodiments of FIGS. 4, 5, 7, and 8 as greater than the gate width ofthe write transistors 116 and 118, or the second driver transistor 126of the core cell 102 sharing the same gate poly. Since the drive currentof a transistor is proportional to the channel width divided by the gatelength, expressed as

Idrive ∝W/L,

the read driver transistor 208 has a larger maximum drive current thandoes the read transistor 207, the write transistors 116 and 118, or thefirst and second driver transistors 120 and 126. In this manner, readdriver transistor 207 has a larger maximum drive current than does thedriver transistor 126, and a faster read operation is provided thanwould be the case if the driver transistor 126 were used as a readdriver transistor. In addition, the gate length (Y-axis in the Figures)of the read transistor 207 (or read driver transistor 208) is drawnshorter than the gate length of the write transistor 118, providing agreater read current for the read transistor 207 than would be providedwith the write transistor 118. Alternatively, or in combination with thelower gate length, the threshold voltage of the read transistor 207(and/or read driver transistor 208) may be designed to be lower thanthat of the write transistor 118 and driver transistor 126 to result ina faster turn-on of the read transistor 207 as well as higher readcurrent. Those skilled in the art of SRAM design will recognize thatthese design options may be combined as desired to meet the designconstraints of the circuit.

Since the read transistor 207 of the present invention advantageouslyhas a separate read wordline RWL 236, the read wordline voltage (e.g.,RWL 310) may be boosted above the level of Vdd 140, for example, toprovide a greater Idrive of the read transistor 207 than would beotherwise possible alone with write transistor 118, such as is only usedin the prior art during read operations and driven by a lowerconventional wordline voltage as limited by the stability of the cell.Thus, read transistor 207 may have a correspondingly narrower gate widthas is illustrated in FIGS. 4, 5, 7, and 8, while still providing thegreater Idrive and faster turn-on.

In the embodiment of FIG. 4, the gate lengths of the transistors makingup the cross-coupled inverters (e.g., the driver transistors 124, 126,and the load transistors 120, 122), and the WRITE transistors 116 and118 are advantageously drawn longer than the minimum gate lengthavailable in the semiconductor technology being used, to reducevariability either from process variation or from any random variationin channel doping. Such variation in the transistors of thecross-coupled inverters and the WRITE transistors can significantlyincrease the likelihood of upsetting the state of the SRAM core cellwhen the cell is accessed. Analogous variation in the read transistor207 and read driver transistor 208 does not have such a seriousdegrading effect, as the read current (e.g., Iread 266) is isolated fromthe latch nodes 104 and 106 of the core cell 102. Thus, transistors 207and 208 can advantageously be designed with minimum gate length.

The exemplary physical layout 870, of FIG. 8 further illustrates adifferential read configuration in a 10T SRAM cell, designed inaccordance with the principles of the present invention, the cellcomprising a complementary pair of read buffers 204 and 205. Layout 870,for example, illustrates read buffer 204 gated by an output of a latch(e.g., 102), where the output of the latch is coupled to the read buffer205 by an extension of the gate of the second driver 126, andcomplementary read buffer 205 gated by an output of the latch (e.g.,102), where the output of the latch is coupled to the read buffer 205 byan extension of the gate of the first driver 124. Other elements oflayout 870 are similar to those of FIGS. 4-7 and need not be fullydescribed again for the sake of brevity.

Thus, FIGS. 4-8 represent a few of the possible layout embodiments ofthe present invention, wherein the maximum drive current Idrive isincreased to provide a faster read access time, or the threshold voltageof the read transistor 207 (and/or read driver transistor 208) may bedesigned to be lower than that of the write transistors 116 and 118 toresult in a faster turn-on of the read buffer transistors 207 and 208.In accordance with the layouts illustrated and the spirit of the presentinvention, the increased drive current Idrive, may be accomplished usingany combination of a shorter gate length, and/or a greater gate width ofthe read buffer transistors 207 and 208 relative to the transistors ofthe 6T core cell 102. Further, the increased Idrive may be enhanced withrespect to the read transistors (e.g., 207, or 207 and 229) with aboosted read wordline voltage 310, as in FIG. 3B.

FIG. 9A illustrates an alternate embodiment of a single sided 8T SRAMcell 900, having a read buffer to isolate the read current from a datanode of the 6T SRAM cell similar to that of FIG. 1A during a readoperation, wherein the read transistor of the read buffer and the writetransistor of the core cell share a common word line, according toanother aspect of the present invention.

Similar to the 8T SRAM cell 200 of FIG. 2A, the 8T SRAM cell 900 of FIG.9A comprises a data cell or core cell 102 as part of a conventional 6TSRAM cell 101, and a read buffer 904. Read buffer 904, like read buffer204 comprises a read transistor 207 and a read driver transistor 208series connected between a read bitline RBL 934 and a source voltage150. Unlike read buffer 204, however, read buffer 904 has the readtransistor 207 gated by a shared wordline WL 932, which thereforejointly controls read and write operations with a shared wordlinesignal. Although, this system has the advantage of one less wordlinethan the cells previously described in the context of the presentinvention, the read transistor 207 cannot take advantage of a beneficialread boosted voltage while holding the wordline for the core cell 102 toa low or Vss voltage. However, the circuit of SRAM cell 900 still hasthe advantage of having an isolated and increased read current Ireadcapability such as by wider width, shorter gate length, or lower Vttransistors in the read circuit compared to the transistors in the core6T cell 101, with the potentially faster read access time previouslydescribed.

FIG. 9B illustrates an alternate embodiment of a single sided 8T SRAMcell 950, similar to the 8T SRAM cell 900 of FIG. 9A, further comprisinga Vss clamp diode connected between a source terminal of the core celland a source voltage (Vss), according to one or more aspects of thepresent invention. The 8T SRAM cell 950 of FIG. 9B combines some of thefeatures of those of FIG. 2B and those of FIG. 9A, and as such need notbe fully described again for the sake of brevity. Again, cell 950comprises a latch 102 that uses the read buffer having read drivertransistor Q8 208 and read transistor Q7 207 to remove the read current(e.g., Iread 264) from the first or second data nodes 104 and 106,respectively, during a read operation. The read buffer 904 of cell 950again comprises a read transistor 207 and a read driver transistor 208series connected between a read bitline RBL 934 and a source voltage150. Also, read buffer 904 has the read transistor 207 gated by a sharedwordline WL 932, which therefore jointly controls read and writeoperations with a shared wordline signal.

Additionally, cell 950 adds a transistor Q9 219 as a VSS clamp diodeconnected between a source terminal (e.g., Vss-Array 255) of the core ordata cell 102 and a source voltage Vss 150. Transistor Q9 219 may beshared among the many 8T cells 250 in an SRAM array, such as array 290of FIG. 2E. More generally, a VSSA is supplied to the array, where VSSAis >VSS of the write BL driver. Thus, the BL can be driven lower ornegative relative to VSSA. In this embodiment of the present invention,the array-Vss 255 may be raised in conjunction with a relatively lowwrite word line voltage 932 to enable a WRITE without upset of cells inunaddressed columns. For read operations, the read WL can be highrelative to the write WL voltage to compensate for the impact of araised Vss (e.g., Vss-Array 255) on the read current (e.g., Iread 264).

For example, the Vss is raised to VSSA by a Vss supply circuit 256, suchas by Q9 219 used as a clamp diode. Alternately, a Vss supply circuit256, such as transistor Q9 219 may be included in every SRAM memory cell250 of the array as is illustrated in array 280 of FIG. 2D.

The exemplary 8T SRAM cell 950 embodiment of FIG. 9B comprises threebitlines (e.g., write bitline WBL 130, write bitline bar WBLB 131, andread bitline RBL 934) and one wordline (e.g., word line WL 932) or(3BL/1WL). Note that in this embodiment, however, that the read WL isunable to compensate for the high VSSA impact on the read current,because the read and write wordlines are not separate to provide arelatively higher voltage on the read WL than the write wordline.

Other such cell and transistor technology variations, including arrayorientation variations are anticipated in the context of the presentinvention.

The invention is also not limited to the use of silicon wafers, and maybe implemented in association with the manufacture of varioussemiconductor devices, SRAM memory devices, or other such devices,wherein the design and optimization of an SRAM cell, potential dataupsets, and power consumption is an issue, where cell access is to belimited only to the memory area being used, wherein cell size andpatterning considerations are problematic, and wherein the variousaspects thereof may be applied.

Although the invention has been illustrated and described with respectto one or more implementations, equivalent alterations and modificationswill occur to others skilled in the art upon the reading andunderstanding of this specification and the annexed drawings. Inparticular regard to the various functions performed by the abovedescribed components (assemblies, devices, circuits, systems, etc.), theterms (including a reference to a “means”) used to describe suchcomponents are intended to correspond, unless otherwise indicated, toany component which performs the specified function of the describedcomponent (e.g., that is functionally equivalent), even though notstructurally equivalent to the disclosed structure which performs thefunction in the herein illustrated exemplary implementations of theinvention. In addition, while a particular feature of the invention mayhave been disclosed with respect to only one of several implementations,such feature may be combined with one or more other features of theother implementations as may be desired and advantageous for any givenor particular application. Furthermore, to the extent that the terms“including”, “includes”, “having”, “has”, “with”, or variants thereofare used in either the detailed description and/or the claims, suchterms are intended to be inclusive in a manner similar to the term“comprising.”

1-14. (canceled)
 15. An integrated circuit including: an SRAM cellcomprising: a first inverter comprising a first load transistor and afirst driver transistor, the first inverter having a first input formedby a connection between a gate of the first load transistor and a gateof the first driver transistor, and having a first output formed by aconnection between a first source or drain of the first load transistorand a first source or drain of the first driver transistor; a secondinverter comprising a second load transistor and a second drivertransistor, the second inverter having a second input formed by aconnection between a gate of the second load transistor and a gate ofthe second driver transistor, and having a second output formed by aconnection between a first source or drain of the second load transistorand a first source or drain of the second driver transistor; the secondinput being connected to the first output, and the second output beingconnected to the first input; a first write transistor connected betweenthe first output and a write bit-line, and having a gate connected to awrite wordline; and a second write transistor connected between thesecond output and a complementary write bit-line, and having a gateconnected to the write wordline; and an assist circuit comprising: afirst assist circuit transistor having a first source or drain connectedto a read bit-line, and a gate connected to a read wordline or the writewordline; and a second assist circuit transistor having a gate connectedto one of the first and second outputs, a first source or drainconnected to a second source or drain of the first assist circuittransistor, and a second source or drain connected to a second source ordrain of each of the first and second driver transistors.
 16. Thecircuit of claim 15, wherein the first and second load transistors arepMOS transistors and the first and second driver transistors are nMOStransistors.
 17. The circuit of claim 16, wherein the first and secondwrite transistors are nMOS transistors.
 18. The circuit of claim 17,wherein the first assist circuit transistor and the second assistcircuit transistor are nMOS transistors.
 19. The circuit of claim 18,wherein the first assist circuit transistor gate is attached to the readwordline.
 20. The circuit of claim 18, wherein the first assist circuittransistor gate is attached to the write wordline.
 21. The circuit ofclaim 18, wherein the second assist circuit transistor gate is connectedto the first output.
 22. The circuit of claim 21, further including avoltage supply circuit comprising a diode-configured transistorconnected between a supply voltage node and the second source or drainof each of the first and second driver transistors.
 23. The circuit ofclaim 15, wherein the first assist circuit transistor and the secondassist circuit transistor are nMOS transistors.
 24. The circuit of claim23, wherein the second assist circuit transistor gate is connected tothe first output.
 25. The circuit of claim 23, further including avoltage supply circuit comprising a diode-configured transistorconnected between a supply voltage node and the second source or drainof each of the first and second driver transistors.
 26. The circuit ofclaim 15, further including a voltage supply circuit comprising adiode-configured transistor connected between a supply voltage node andthe second source or drain of each of the first and second drivertransistors.
 27. The circuit of claim 15, wherein the first assistcircuit transistor gate is attached to the read wordline.
 28. Thecircuit of claim 15, wherein the first assist circuit transistor gate isattached to the write wordline.
 29. An integrated circuit including: anSRAM cell comprising: a first inverter comprising a first loadtransistor and a first driver transistor, the first inverter having afirst input formed by a connection between a gate of the first loadtransistor and a gate of the first driver transistor, and having a firstoutput formed by a connection between a first source or drain of thefirst load transistor and a first source or drain of the first drivertransistor; a second inverter comprising a second load transistor and asecond driver transistor, the second inverter having a second inputformed by a connection between a gate of the second load transistor anda gate of the second driver transistor, and having a second outputformed by a connection between a first source or drain of the secondload transistor and a first source or drain of the second drivertransistor; the second input being connected to the first output, andthe second output being connected to the first input; a first writetransistor connected between the first output and a write bit-line, andhaving a gate connected to a write wordline; and a second writetransistor connected between the second output and a complementary writebit-line, and having a gate connected to the write wordline; a firstread circuit comprising: a first read transistor having a first sourceor drain connected to a read bit-line, and a gate connected to a readwordline; and a first read driver transistor having a gate connected toone of the first and second outputs, a first source or drain connectedto a second source or drain of the first read transistor, and a secondsource or drain connected to a second source or drain of each of thefirst and second driver transistors; and a second read circuitcomprising: a second read transistor having a first source or drainconnected to a complementary read bit-line, and a gate connected to theread wordline; and a second read driver transistor having a gateconnected to the other one of the first and second outputs, a firstsource or drain connected to a second source or drain of the second readtransistor, and a second source or drain connected to the second sourceor drain of each of the first and second driver transistors.
 30. Thecircuit of claim 29, wherein the first and second load transistors arepMOS transistors and the first and second driver transistors are nMOStransistors.
 31. The circuit of claim 30, wherein the first and secondwrite transistors are nMOS transistors.
 32. The circuit of claim 31,wherein the first and second read transistors and the first and secondread driver transistors are nMOS transistors.
 33. The circuit of claim320, wherein the first read driver transistor gate is connected to thefirst output and the second read driver transistor gate is connected tothe second output.
 34. The circuit of claim 29, wherein the first andsecond read transistors and the first and second read driver transistorsare nMOS transistors.